Monday, July 11, 2011

Power Transistors

Power Transistors
A power transistor is one that is capable of handling 1 W or more of power or drawing 1 A or more of current during normal operation without being damaged. Power transistors are used in such applications as amplification, oscillation, switching, and frequency conversion. The three small-signal transistor geometries adapted as power transistors are: (1) the BJT, (2) the Darlington pair, and (3) the MOSFET.


A power BJT has a geometry similar to that of a discrete small-signal transistor. Most power BJTs have vertical geometries, with the bases and emitters grown on top of the substrate, which functions as the collector. There are both NPN and PNP power transistors. In the absence of a universal power BJT design that will perform all power functions equally well, many different variations have been developed to provide a range of electrical and thermal characteristics for different applications. Each design has advantages and disadvantages or tradeoffs. These structural variations can be classed by the number of diffused layers, the use of an epitaxial base, or combinations of these. BJTs can be made with mesa or planar structures. Some common power bipolar structures are:

■ Single-diffused (hometaxial)
■ Double-diffused (mesa, planar, epitaxial mesa, planar mesa, and multiple epitaxial mesa)
■ Triple-diffused (mesa and planar)
■ Epitaxial base (mesa)
■ Multiple epitaxial base (mesa)

A mesa is a raised section of the die, with the emitter and base geometry in relief above the level of the silicon collector substrate. The mesa is formed by selectively chemically etching away all but the corners of a completed double-diffused die. A planar transistor is made in basically the same way as the mesa version, but the collector-base junction terminates under a protective oxide layer at the surface. Power transistors made with these topologies have different voltage ratings, switching speeds, saturation resistances, and leakage currents. The most advanced switching BJTs have multiple epitaxial, doublediffused structures.

Power bipolar transistors are specified by determining the required values for the following parameters:

■ Voltage rating, collector to emitter
■ Current rating of the collector
■ Power rating
■ Switching speed
■ DC current gain
■ Gain-bandwidth product
■ Rise and fall times
■ Safe operating area (SOA)
■ Thermal properties

The popularity of the switching-regulated or switch mode power supply created a demand for power bipolar transistors capable of switching at frequencies in excess of 10 kHz. To qualify for this application, the power transistor must be able to withstand voltage that is typically twice its input voltage. It must also have collector current ratings and safe operating areas that are high enough for the intended application.

A bipolar transistor operated at high power densities is subject to second breakdown failure which occurs when a thermal hot-spot forms within the transistor chip and the emitterto-collector voltage drops 10 to 25 V. Unless power is quickly removed, current concentrates in the small region and temperatures rise until the transistor is damaged or destroyed.

Safe operating area (SOA) is defined by a graph that indicates the ability of a power transistor to sustain simultaneous high currents and high voltages. It is the plot of collector current versus collector-to-emitter voltage. The curve defines, for both steady-state and pulsed operation, the voltage-current boundaries that result from the combined limitations imposed by voltage and current ratings, the maximum allowable dissipation, and the second breakdown limitations of the transistor.


A high-electron-mobility transistor (HEMT) is a GaAs transistor designed for IC integration. As shown in Fig. 2-13, it is fabricated on a layer of aluminum gallium arsenide (AlGaAs) grown on a GaAs substrate. This heterojunction design improves transistor performance and permits even higher levels of integration than are possible with the MESFET.

 High-electron-mobility transistor (HEMT).


A heterojunction bipolar transistor (HBT) is a bipolar GaAs transistor grown on a heterojunction. Heterojunction E/D technology was developed to achieve cost-effective GaAs digital large-scale integrated (LSI) and very large scale integrated (VLSI) devices. The structure, shown in Fig. 2-14, permits high levels of integration. Both HEMTs and HBTs require special processing to achieve precise, sharp heterojunctions.

Gallium-Arsenide Transistors

The geometries of silicon BJTs and MOSFETs have been implemented in gallium arsenide (GaAs) to take advantage of the higher speed and operating frequencies made possible by the substitution of GaAs silicon. Because GaAs is a compound semiconductor material, it does not form natural oxides as silicon does, so this made it necessary to alter the silicon device geometries to devise different manufacturing methods.

Metal semiconductor field-effect transistor (MESFET).

Three different gallium arsenide transistor designs have been developed: (1) metal semiconductor field-effect transistor (MESFET), high-electron-mobility transistor (HEMT), (3) heterojunction bipolar junction transistor (HBT).


The metal semiconductor field-effect transistor (MESFET) is a widely used discrete and integrated-circuit GaAs transistor geometry. Its structure is similar to that of a MOSFET, but its metal gate is deposited directly on the doped GaAs substrate, as shown in Fig. 2-12, to form a Schottky barrier diode. However, silicon oxides are deposited on the substrate for isolation and insulation. The length of the metallized gate (positioned between the source and drain) is critical in both discrete GaAs transistors and ICs.

Typically 0.5 to 1.0 μm in most discrete transistors, it could be as small as 0.2 μm in ICs. But the gate structure is usually much wider with respect to its length—typically 900 to 1200 μm. MESFETS can have interdigitated structures with multiple gates formed as comblike structures. Ion implantation is favored for doping active regions of MESFETs. A 0.1- to 0.2-μm-thick N-doped region is made for the most common depletion-mode MESFETs (D-MESFETs). The enhancement-mode MESFET (E-MESFET) and the enhancement-mode JFET (E-JFET) are other GaAs transistors that have been developed. Both E-MESFETs and D-MESFETs can be combined in ICs to form enhancement/ depletion-mode (E/D) logic.

Friday, July 9, 2010


An enhancement-mode MOSFET is normally off because it requires a gate bias signal to cause current flow because of the high impedance of its substrate source-to-drain channel.In the N-channel enhancement-mode MOSFET shown in Fig. 1a, the substrate is P-type silicon and both the source and drain regions are heavily doped N-type silicon. The metal gate, the insulation layer, and the channel act like a capacitor, so if a bias is placed on the gate, a charge of opposite polarity will appear in the channel below it. For example, if the drain voltage is positive with respect to the source voltage, and the bias on the gate is zero, no current will flow.

But, if the gate is then made positive, negative charge carriers (electrons) are induced in the channel between the source and drain regions. Further increases in positive bias induce more electrons into the channel, where they accumulate to form an N-type channel between source to the drain. The value of drain current depends on channel resistance, so gate voltage controls drain current. Because channel conductivity is enhanced by a positive gate bias, the transistor is called an enhancement-mode MOSFET.

Figure 1b shows the schematic symbol for an N-type enhancement-mode MOSFET. The vertical line connected to the gate pin represents the gate, and the broken lines connected to the drain and source pins indicate that a channel does not exist until a gate voltage is applied. The arrowhead representing conventional current points from the P-type substrate to the induced N-type channel

A P-channel enhancement-mode MOSFET has the same geometry as the N-channel enhancement-mode MOSFET except that both the material dopants and the applied voltage polarities are reversed. Its schematic symbol is identical except that the direction of the arrowhead is reversed.

Figure 1 Enhancement-mode N-channel MOSFET: (a) section view, and (b) symbol.


The metal-oxide semiconductor FET (MOSFET) offers a higher input impedance than a JFET. A section view of an N-channel MOSFET is shown in Fig. 1a. An insulating layer of silicon dioxide is grown on top of the region between the N-type source and the N-type drain. The gate is electrically isolated from the source and gate contacts and the source to-drain channel beneath it. The schematic symbol for an N-channel MOSFET is shown in Fig. 1b. The two kinds of MOSFETs are enhancement mode and depletion mode. The depletion-mode MOSFET has a lightly doped source-to-drain channel, whereas the enhancement-mode version does not.

Figure 1 Metaloxide semiconductor FET (MOSFET): (a) section view, and (b) symbol.


The N-channel junction FET (JFET), shown in section view Fig.1a, has an N channel diffused into a P-type substrate and a P-type region diffused or implanted into the N channel to form the P-type gate. Metal deposited directly on the gate, source, and drain regions forms their contacts. Because a JFET has a symmetrical structure, the drain and source are interchangeable. Thus, depending on the location of the ground and the +V power source, the JFET will work in either direction.

Figure 1 Junction field-effect transistors (JFETs): (a) N-channel section view

If a positive voltage is applied at the drain contact and a negative voltage is applied at the source contact with the gate contact open, a drain current flows. If the gate is then biased positive, channel resistance decreases and drain current increases. However, if the gate is biased negative with respect to the source, the PN junction is reverse biased and a depletion region depleted of charge carriers is formed. Because the N-type channel is more lightly doped than the P-type silicon, the depletion region penetrates into the channel, effectively narrowing it and increasing its resistance. If the gate bias voltage is made even more negative, drain current is cut off completely. A gate bias voltage value that will cut off the drain current is called the pinch-off or gate cutoff voltage. The schematic symbol for an N-channel JFET is shown in Fig. 1b. The arrow points from the P-type gate to the N-type channel.

(b) N-channel symbol, (d) P-channel symbol

The P-channel JFET, shown in Fig. 1c, has characteristics similar to those of the N-channel JFET except that the polarities of the voltage and current are reversed. A P-type channel is diffused into an N-type substrate and then an N-type gate region is diffused or implanted into the P-channel to form the N-type gate. If a negative voltage is applied to the drain and a positive voltage is applied to the source, current flows between source and drain. But if the gate is made more negative more current will flow, while if it is made positive with respect to the source, current will be cut off.

(c) P-channel section view

The schematic symbol for a P-channel JFET is shown in Fig. 1d. The arrow points from the P channel to the N gate.

Field-Effect Transistors

A field-effect transistor (FET) is a voltage-operated transistor. Unlike a BJT, a FET requires very little input current, and it exhibits extremely high input resistance. There are two major classes of field-effect transistors: junction FETs (JFETs) and metal-oxide semiconductor FETs (MOSFETs), also known as insulated-gate FETs (IGFETs). FETs are further subdivided into P- and N-type devices. FETS are unipolar transistors because, unlike the BJT, the drain current consists of only one kind of charge carrier: electrons in N-channel FETs and holes in P-channel FETs.

FETs and MOSFETs are both made as discrete transistors, but MOSFET technology has been adopted for manufacturing power FETs (see “Power Transistors” later in this section) and ICs. There are both NMOS and PMOS ICs. When both P- and N-channel MOSFETs are integrated into the same gate circuit, it is a complementary MOS (CMOS).